1. Field of the Invention
The present application relates to programmable resistance memory, including phase change memory, and more particularly to a write cycle for a memory device.
2. Description of Related Art
In a phase change memory and other programmable resistance memory, to write a data value represented by a resistance range to a memory cell, a sequence of alternating verify operations and write operation can be applied to the memory cell. A phase change memory can be a bit-alternative memory, where a verify operation and a write operation to set a first memory cell to a first resistance range can be in the same write cycle as a second verify operation and a second write operation to set a second memory cell to a second resistance range. To write two data values represented by two different resistance ranges to two memory cells, verify operations on the two memory cells can both start at an initial time, and subsequent write operations on the two memory cells can both start at a second time, in the same write cycle. However, depending on the data value, a verify operation is either longer or shorter than a write operation. Consequently, a longer write operation after a shorter verify operation on a first memory cell waits for a longer verify operation on a second memory cell to end before the longer write operation on the first memory cell can start. Similarly, the longer verify operation after the shorter write operation on the second memory cell waits for the longer write operation on the first memory cell to end before the longer write operation for the second memory cell can start. Such waiting degrades the overall memory performance.
It is desirable to provide a method to improve the overall memory performance when writing data values represented by different resistance ranges in the same write cycles.